Free Tools for free Hardware
Hagen Sankowski
hsank@nospam.chipforge.org
Introduction
The Free Software Definition
Free software is a matter of the users' freedom to run, copy, distribute, study, change and improve the software. More precisely, it refers to four kinds of freedom, for the users of the software:
- The freedom to run the program, for any purpose.
- The freedom to study how the program works, and adapt it to your needs.
- The freedom to redistribute copies so you can help your neighbour.
- The freedom to improve the program, and release your improvements to the public, so that the whole community benefits.
(c) Free Software Foundation
It doesn't mean:
- tools shipped without Source Code
- limited trail or evaluation versions
- shareware, public domain or other such stuff which allways is proprietary
A "Open Source Initiative" (OSI) certified licence is a precondition!
Electronic Design Automation (EDA)
- Tools for Designing and Producing Electronic Systems
- ranging from Printed Circuit Boards (PCBs) to Integrated Circuits (ASICs)
Spice
- general purpose analog circuit simulator
- developed at University of California, Berkeley in 1975
- a lot of proprietary and free branches, re-implementations etc.
- also a synonym for *the* analog netlist format
Verilog
- Hardware Description Language (HDL)
- used for the digital design of ASICs and FPGAs
- developed at Gateway Design Automation in 1985
- purchased by Cadence Design Systems in 1990
- after increasing success of VHDL submitted to IEEE
- became IEEE Standard 1364-1995, now updated to IEEE Standard 1364-2001
[Personal Statement: I'm 10 times more productive in Verilog than in VHDL. But I love too the nice features of VHDL like type definition, resolution function, generate etc.]
VHSIC Hardware Description Language (VHDL)
- also used for the digital design of ASICs and FPGAs
- developed at the US Department of Defense to document the behaviour of ASICs
- initial version of VHDL designed to IEEE Standard 1076-1987
- lack of types required IEEE Standard 1164, which defined 'std_logic_1164' package
- later syntax updated within IEEE Standard 1076-1993
[Personal Statement: With VHDL you can simulate everything, the weather too. But who wants?]
Design Flow
High Level Entry
behavioral Description on a high level
- Finite State Machine (FSM)
- Register Transfer Level (RTL)
or as Schematic
Simulation
based on the High Level Entry
- check the design with challenging stimuli
- otherwise here is the cheapest place to test & debug
[Don't go further without any successfull simulation!]
[This means, your testbench has the highest value of work you've ever did on your design!]
Netlist
generate netlist
- in Spice for analog and mixed-signal designs
- in VHDL or Verilog for digital designs
- the process usually called synthesis
Re-Simulation
repeat simulation
- with the current netlist
- it should be mandatory
Place & Route (P&R)
virtual on Computer
- for PCB and Silicon
- sophisticated process
Design Rule Check (DRC)
mind good rules for a good design
- mostly depending on technology
- keep in contact with the fab
Parasitics Modelling
modelling all parasitics you know
- analog: wire model (width and length, spaces between, vias etc)
- digital: timing model (delay over long lines)
Re-Simulation
a design you don't stress doesn't work
- re-simulate your design, parasitics model included
Production
generate fab-ready files
- PCB: Gerber etc.
- ASIC: GDS II
- FPGA: Bitstream
Test
generate stimuli & response testpattern
- generate pattern for all testcases you've written
free Tools
GUI/Project Manager
- geda
- kicad
Schematic Capture
- gschem
- kicad
Netlist Generation
- gnetlist
- iverilog
[iverilog is able to generate EDIF netlists!]
Simulation
- ngspice
- iverilog
- ghdl
- freehdl
[ghdl and freehdl uses the gcc to compile executable programms]
[ghdl goes therfore into the gcc backend, ready to link; freehdl just generate C code]
[compilation generate a file to run, like "./tc_reset" with some options]
Simulation Example: iverilog
[make controll nearly everything, in this case you may see make + testcase name]
[use of a failure counter is a good way to know wether the testcase was passed or failed]
[see last line with testcase name and *well done* you may grep over logfiles]
Waveform Viewer
- gtkwave
- gwave
[GTKwave has problems with sophisticated VHDL typing. Keep typing simple, if you plan to use GTKwave]
[gwave just belongs to analog simulations]
Waveform Example: GTKwave
[the same testcase as seen with iverilog]
Printed Circuit Boards
- gsch2pcb
- pcb
- kicad
[kicad seams to be still buggy in case of export into align file formats. Or otherwise spoken, proprietary tools got trouble reading exported files from kicad]
VLSI tool suites
- alliance
- electric
- magic
- ivi
[alliance and electric are more or less complete]
[magic is just a layout tool]
[ivi is just a GUI for Icarus Verilog and GHDL]
-still missing-
- Autorouter for PCBs
- Design Rule Checker for PCB
- Synthesizer / Netlist Generator for VHDL
- Place & Route for FPGAs
[theres the big need for the autorouter for PCBs!]
[place & route for FPGAs is out of scope, 'cause the bitstreams for the two big players on FPGA market, Xilinx and Altera, are closed. Reverse Engineering isn't a legal act!]
Links
- www.opencollector.org - good starting point for tool research
- www.geda.seul.org - gEDA Tool Suite
- www.lis.inpg.fr/realise_au_lis/kicad - Schematic & PCB artwork
- icarus.com/eda/verilog - Icarus Verilog Simulator and Netlist Generator
- ghdl.free.fr - VHDL Simulator
- www.freehdl.seul.org - VHDL Simulator
- www.staticfreesoft.com - The Electric VLSI Design System
- www-asim.lip6.fr/recherche/alliance - Alliance the free VLSI cad system
- bach.ece.jhu.edu/~tim/programs/magic - Magic VLSI layout tool
[please check the top links first.]
Thanks for listening!
please feel free to ask..
[I'll update the foils in the next time with all stuff belongs to your questions.]